Features

Portable

Described in behavioral VHDL
Easily integrated into Verilog and VHDL based designs
Usable on virtually any FPGA, not tied to any particular vendor

Optimized for FPGA

3-stage hazard-free pipeline
256 registers implemented as a RAM block
Only 30 distinct opcodes
Clock frequencies of 100 MHz and above are achievable on most modern FPGAs

Harvard architecture

Separate instruction and data buses
WISHBONE compatible
Can use on-chip or external RAM

Configurable

Three multiplier options
Optional instruction cache
Optional divider

Proven

Comes with a verification environment (self-checking testbench)
Used in commercial projects
OpenCores Certified Project

Open source

Permissive MIT license, friendly for commercial use
Open source simulation is available using GHDL

Download

The latest version of the LXP32 soft microprocessor, 1.4, was released on 2024-11-02.

lxp32-cpu-1.4.7z

The package includes:

synthesizable RTL description of the CPU
documentation
automated verification environment (self-checking testbench)
software development tools (assembler/linker, disassembler) with source code
configurable WISHBONE interconnect generator

The LXP32 instruction set architecture doesn't have a compiler backend yet, only assembly based workflow is supported. This makes LXP32 more useful in a small bare metal SoC running from on-chip RAM.

Documentation

The LXP32 soft CPU core comes with a comprehensive and up-to-date manual which contains all the information needed to integrate the processor into your design and develop software for it:

LXP32 CPU Technical Reference Manual